Data error detection techniques are well known in digital data communications, with the simplest of these being parity checking. A failing of the parity checking technique is that if more than one data bit is received in error, the errors could be self defeating and the parity check may falsely be held to be correct.
An improvement of the simple parity check is to do a parity check in two dimensions. This is commonly known as a longitudinal redundancy check. This system is also not fail-safe, as errors in two bits of one word and errors in the same bits of another word will not be detected.
A further known system is the checksum technique, where the binary values of all data bits are added together (discarding overflows) and sent with the data. As before, two errors in the same bit in different data words can cause an error not to be detected.
An improvement on the former techniques is the so-called cyclic redundancy checking (CRC) technique. This technique takes data bits in each data word and performs a unique logical operation on those bits, usually determined by a higher order polynomial formula. The result of this operation is a binary check character (BCC), which is then appended to the data bits for transmission.
At the receiver, the same routine is performed on the received data bits and the result is then compared to the received BCC. If the two BCC's are in error, there is scope for error correction by subsequent bit reversal of suspect data bits, however, if the BCC itself is in error, then the correct data word can not be determined. The cyclic redundancy check, if incorrect, requires substantial processing power in order to complete the necessary computations to attain correction before the arrival of a subsequent data word.
Other data error correction techniques such as forward correction are known. These techniques require powerful processing to cope with the large amount of redundant information that necessarily must be included in order that the correction can be performed. Once the processing power required increases, so to does the complexity, size and cost of the integrated circuitry by which it is implemented.
A number of earlier communication systems have addressed in a different manner the problem of determining whether a received RF waveform might contain errors. These systems are concerned primarily with the signal to noise ratio of the decoder input signal, which, if below a certain value is thought to indicate the presence of suspect bits.
Deficiencies in such systems are firstly, that in the detection process (typically involving an amplitude detection circuit having elements such as diodes, resistors and capacitors), decoded bits are delayed in time for many bit periods due to the smoothing effect of the detection circuit, thus making correlation between a suspect bit and the baseband signal during the instant of that bit uncertain. Secondly, there are questionable relations between the baseband signal to noise ratio and the decode quality. The presence of noise may enhance the received waveform rather than degrade it depending on the characteristics of the noise itself, thus making the detecting of suspect bits unreliable.
The present invention attempts to overcome problems inherent with the known devices and techniques, by providing a simplified error detection system, not requiring the substantial processing power of prior art systems.